1. Field of the Invention
This disclosure relates to a semiconductor device manufacturing field, and in particular relates to a method of forming a gate pattern and a semiconductor device having the gate pattern.
2. Description of the Related Art
It is often needed to form a gate pattern as shown in FIG. 1 in semiconductor integrated circuits. More specifically, such a gate pattern comprises a plurality of gate bars parallel to each other in a first direction, and each gate bar is broken up by gaps.
In a modern semiconductor manufacturing process, as the size of semiconductor devices deceases, the gate pattern is generally hard to be formed by a single patterning. Therefore, in order to form the gate pattern as shown in FIG. 1, a double patterning technique is employed widely.
FIGS. 2A-2D schematically illustrate a method of forming the gate pattern by employing a conventional double patterning technique.
First, as shown in FIG. 2A, a resist pattern 210, which has a plurality of openings parallel to each other and extending continuously, is formed by a first patterning process. Next, as shown in FIG. 2B, a first etching process is performed with the resist pattern 210 as a mask so as to form on a substrate 250 a plurality of gate material bars 260 parallel to each other and extending continuously. Then, as shown in FIG. 2C, a resist pattern 220 having trimming slots is formed by a second patterning process. The positions of the trimming slots correspond to the positions of the gaps breaking up the gate bars. Finally, as shown in FIG. 2D, a second etching process is performed with the resist pattern 220 as a mask so as to form the gaps in the plurality of gate material bars 260 parallel to each other which are obtained after line etching, thereby the gate pattern as shown in FIG. 1 is formed.
The present inventors have conducted in-depth investigation on the above method of forming the gate pattern, and have found that there exist some problems.
For example, as the size of semiconductor devices keeps decreasing, the obtained trimming slot patterns deviate from the designed patterns due to a margin of trimming slot patterning. Furthermore, after performing trimming slot etching by using the deviated trimming slot patterns, deviation between the obtained gate pattern and the designed pattern is more remarkable, whereas it is very difficult to modify such deviation. In this way, the shape and size of the gate pattern cannot be accurately controlled, thereby an adverse effect on the performance of semiconductor devices is caused.